Testability-Driven Layout of Combinational Circuits
نویسندگان
چکیده
منابع مشابه
Layout Driven Synthesis of Lattice Circuits
When the design process of digital circuits is carried out in individual step (like logic minimization, mapping and routing) we may suffer quality loss. Typical examples thereof are cases where a highly optimized netlist fits badly onto the target architecture or when interconnection delays violate the given timing constraints. Therefore we seek a unified synthesis methodology, allowing the log...
متن کاملLayout Driven Synthesis of Lattice Circuits
When the design process of digital circuits is carried out in individual step (like logic minimization, mapping and routing) we may suffer quality loss. Typical examples thereof are cases where a highly optimized netlist fits badly onto the target architecture or when interconnection delays violate the given timing constraints. Therefore we seek a unified synthesis methodology, allowing the log...
متن کاملSynthesis for Full Testability of Partitioned Combinational Circuits Using Boolean Diierential Calculus
| Synthesis for testability has been taken as an important topic of research and application. Tools for synthesis of fully testable circuits have been developed. These design tools are faced with an ever increasing complexity. Methods to partition large logics into parts and synthesis of each sublogic independently have been provided from different points of view recently. However, a large circ...
متن کاملResynthesis of combinational logic circuits for improved path delay fault testability using comparison units
We propose a resynthesis method that modifies a given circuit to reduce the number of paths in the circuit and thus improve its path delay fault testability. The resynthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. A subcircuit can be replaced by a comparison unit if it implements a function belonging to the class of comparison func...
متن کاملResynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Reduction and for Path Delay Fault Testability Angela Krsti c and Kwang-Ting (Tim) Cheng Department of ECE, University of California, Santa Barbara, CA 93106 Abstract Path delay fault model is the most suitable model for detecting distributed manufacturing defects that can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability o...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: VLSI Design
سال: 1998
ISSN: 1065-514X,1563-5171
DOI: 10.1155/1998/10193